Zilog Z08470 - Manual (Page 119)

< %27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601 Direct Memory Access

Starting Address (Port B)
The starting address for Port B in the next two bytes may be specified by
setting bits 2 and 3 of the base register to 1. This is only needed if Port B is
used, and then it specifies the first address at which a byte is read from or
written to, depending on whether the port is declared a source or destination
in WR0. If Port B is to be a fixed-address destination, see “Fixed-Address
Destination Ports” on page 121.
Interrupts
Bit 4 of the base register byte can point to the interrupt control byte, and
bits 4 and 3 of the interrupt control byte can point to the interrupt vector and
pulse control bytes, respectively. The interrupt control byte also specifies
one or more of the following three interrupt conditions:
•
Interrupt on match (bit 0), if stop on match or stop on end-of-block is
also programmed
•
Interrupt at end-of-block (bit 1), if stop on end-of-block is also
programmed
•
Interrupt on Ready (bit 6), for example, interrupt before requesting
the bus when the Ready line becomes active
Setting any of these bits to 1 enables the interrupt condition but not the
interrupt circuitry itself, which is enabled either through the ENABLE
INTERRUPTS command in WR6 or through bit 5 in WR3. Interrupts do
not occur on these conditions if their associated bits are 0 in the interrupt
control byte. Table 13 and Table 15 in the previous chapter apply to these
interrupt conditions because the DMA releases the bus (stops) before inter-
rupting the CPU.