Zilog Z08470 - Manual (Page 159)

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UM008101-0601 Direct Memory Access

In an interrupt-driven CPU transfer scheme, the SIO must interrupt the CPU
whenever it has received a character or needs another character to transmit.
A very short benchmark service routine, which assumes the exclusive use of
the Z80 CPU’s alternate register set for SIO interrupt handling, is provided
below.The numbers in parentheses are clock periods per instruction.
Before the service routine can be executed, the CPU must have its inter-
rupts enabled, finish its current instruction, and execute an interrupt
acknowledge cycle (19 clock periods). This optimistic benchmark takes at
least 68 clock periods per byte transferred, and severely restricts CPU
activity by permanently occupying the alternate register set.
To compare these transfer methods, the ratios of clock cycles used per
Kbaud to clock cycles available per second can be calculated. These
DMA I/O write cycle begins 3 latency, bus occupancy
DMA terminates BUSREQ 1 latency, bus occupancy
DMA I/O write cycle ends 1 latency, bus occupancy
CPU terminates BUSACK and
regains control of bus 1 bus occupancy
SIOSVC:
EXX ; get transfer parameters (4)
OUTI ; transfer a byte,
; update parameters (16)
JRZ,BLKEND ; test for end-of-block (7)
EXX ; save parameters (4)
EI ; reenable interrupts (4)
RETI (14)
Table 18. Transmit Event Sequence (Continued)
Event
Inter-event delay
(clock periods)