Zilog Z08470 - Manual (Page 79)

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UM008101-0601 Direct Memory Access

be independently programmed as 2, 3, or 4 clock cycles long (more if Wait
cycles are used), thereby increasing or decreasing the speed at which all
DMA signals change.
Second, the four signals in each port (I/O Request, Memory Request, Read,
and Write) can each have its active trailing edge terminated one-half clock
cycle early. This adds a further flexibility by allowing functions such as
shorter-than-normal Read or Write signals to go inactive before data starts
to change. Figure 24 illustrates the general capability, which is described
later in “Timing” on page 151”
Figure 24. Variable Cycle Length
Events and Actions
Table 10 gives an overview of the events that can cause specific actions by
the DMA, depending on how it is programmed. The events are conditions
in the DMA’s internal registers, signals from the I/O device, or instructions
on the data bus for which the DMA watches.
CLK
T
1
T
2
T
3
T
4
2-Cycle
3-Cycle
4-Cycle
Early Ending
for Control Signals