Zilog Z08470 - Manual (Page 184)

< %27 2GTKRJGTCNU
7UGT /CPWCN
UM008101-0601 Direct Memory Access

Figure 72. RDY Line in Continuous Mode
Variable Cycle and Edge Timing
The Z80 DMA’s operation-cycle length, without Wait states for the source
(read) port and destination (write) port, can be independently programmed.
This variable-cycle feature allows read or write cycles consisting of two,
three, or four clock cycles, more if Wait cycles are inserted, increasing or
decreasing the pulse widths of all signals generated by the DMA. In addi-
tion, the trailing edges of the IORQ, MREQ, RD, and WR signals can be
independently terminated one-half cycle early. See Figure 73 .
A15–A0
D7–D0
RD
MREQ
BUSREQ
BAI
RDY