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7UGT /CPWCN
UM008101-0601
Direct Memory Access
Figure 52.
Simultaneous Transfer
DMA
IORQ RD
WR BUSACK
BAI
RD IORQ
MRD
MWR
HIGH
RD
WR
MEMORY
I/O
DECODER
IOCE
IOWR
IORD
Address and Data Buses
RD WR CE
OE
Y1 Y2 Y3 Y4
SEL
1
0
