Zilog Z08470 - Manual (Page 61)

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7UGT /CPWCN
UM008101-0601 Direct Memory Access

DMA FUNCTIONAL DESCRIPTION
Features
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Single Highly Versatile Channel
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Dual Port Address Generation with Incrementing, Decrementing, or
Fixed Address in Both Ports
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Buffered Address and Block-Length Registers
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64 Kbyte Maximum Block Length
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2.4 or 4 MHz Clock Rates (Z80 or Z80A DMA)
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1.25 or 2 MB/s Data Rate (Z80 or Z80A DMA)
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Transfer, Search, or Transfer/Search Operations
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Bit-Maskable Byte Searching
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Sequential (Flow-Through) or Simultaneous (Flyby) Transfers
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Compatible with Z80 and Many Other CPUs
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Byte, Burst, and Continuous Modes
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Auto Restart Capability
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Variable Cycle Timing
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Wait-Line Cycle Extension
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Internally Modifiable Interrupt Vectors
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Programmable Interrupts on Ready, End-of-Block, Byte Match
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Hardware Priority Daisy-Chains for Bus Requests and Interrupts
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Periodic Pulse Generation for External Device
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21 Writeable Control Registers
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Seven Readable Status Registers