3 chip set overview – Hypertherm SuperMicro 370SBA 533Mhz User Manual

Page 23

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Chapter 1: Introduction

1-13

1-3

Chip Set Overview

440BX Chip Set

The 440BX chip set, developed by Intel, is the ultimate processor platform tar-

geted for 3D graphics and multimedia applications. Along with a System-to-PCI

bridge integrated with an optimized DRAM controller and data path, this chip set

supports the Accelerated Graphics Port (AGP) interface. AGP is a high perfor-

mance, component level interconnect targeted at 3D applications and based on

a set of performance enhancements to PCI. The I/O subsystem portion of the

440BX platform is based on the PIIX4E, a highly integrated version of Intel's PCI-

to-ISA bridge family.

The PCI/AGP and system bus interface controller (82443BX) supports one

Celeron processor. It provides an optimized 72-bit DRAM interface (64 bits of

data plus ECC) that supports 3.3V DRAM technology. The controller provides

the interface to a PCI bus operating at 33 MHz. This interface implementation

is compliant with the PCI Rev 2.1 Specification. The AGP interface is based on

AGP Specification Rev 1.0. It can support data transfer rates of up to 133 MHz

(532 MB/s).

440LX Chip Set

The 440LX chip set, developed by Intel, is a high-performance processor

platform targeted for existing 3D graphics and multimedia applications.

Along with a System-to-PCI bridge integrated with an optimized DRAM

controller and data path, this chip set supports the Accelerated Graphics Port

(AGP) interface. AGP is a high performance, component level interconnect

targeted at 3D applications and based on a set of performance enhancements

to PCI. The I/O subsystem portion of the 440LX platform is based on the

PIIX4, a highly integrated version of Intel's PCI-to-ISA bridge family.

The 440LX PCI/AGP Controller (PAC) system bus interface supports one

Celeron processor. It provides an optimized 72-bit DRAM interface (64 bits of

data plus ECC) that supports 3.3V DRAM technology. The PAC provides the

interface to a PCI bus operating at 33 MHz. This interface implementation is

compliant with the PCI Rev 2.1 Specification. The AGP interface is based on

AGP Specification Rev 1.0. It can support data transfer rates of up to 133

MHz (532 MB/s).

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