EVGA force 132-YW-E178 - Manual (Page 65)

EVGA 54
When you select one of the CPUOC x% options, the FSB - Memory Clock Mode is set to
Unlinked and cannot be changed until SLI-Ready Memory is set to Disable . Please
note when enabling SLI –Ready memory, timings and voltages will change automatically
based on selection.
 FSB and Memory Clock Mode
Use the Page Up and Page Down keys to scroll through the FSB and Memory Clock
Mode options. The options are:
 Auto
This is the optimal setting since it sets the FSB and memory speeds automatically.
 Linked
When Link is selected, FSB (QDR), MHz is changed to editable and the FSB speed
can be entered manually. As the FSB speed is changed, CPU Freq, MHz changes
proportionally.
 Unlinked
When Unlink is selected, FSB (QDR), MHz and MEM (DDR), MHz are changed to
editable and the FSB and memory speeds can be entered manually. As the FSB speed
is changed, CPU Freq, MHz changes proportionally.
 FSB (QDR), MHz
Use the + or – keys to scroll through new values for the CPU FSB frequency or type in a
new value. Note that the Actual FSB (QDR) reflects the actual frequency that takes
effect on a reboot.
 MEM (DDR), MHz
Use the + or – keys to scroll through new values for the memory frequency or type in a
new value. Note that the Actual MEM (DDR) reflects the actual frequency that takes
effect when the system reboots.
FSB – Memory Clock Mode [Linked]
FSB (QDR), MHz [1067] 1066.7
Actual FSB (QDR), MHz 1066.7
MEM (DDR), MHz [1067] 800.6
Actual MEM (DDR), MHz 800.0
CPU Freq, MHz 2933.3 2933.3
CPU Multiplier 11X 11X
FSB – Memory Clock Mode [Linked]
FSB (QDR), MHz [1067] 1066.7
Actual FSB (QDR), MHz 1066.7
x MEM (DDR), MHz Auto 800.6
Actual MEM (DDR), MHz 800.0