ProSoft Technology MVI69-ADM - Manual (Page 45)

MVI-ADM ♦ 'C' Programmable Understanding the MVI-ADM API
'C' Programmable Application Development Module Developer's Guide
ProSoft Technology, Inc. Page 45 of 342
February 20, 2013
Normal Data Transfer
Normal data transfer includes the paging of the user data found in the module’s
internal database in registers 0 to 4999 and the status data. These data are
transferred through read (input image) and write (output image) blocks. The
structure and function of each block is discussed in the following topics.
Block Request from the Processor to the Module
These blocks of data transfer information from the PLC processor to the module.
The following table describes the structure of the output image.
Offset Description Length
0 Write Block ID 1
1 to 60 Write Data 60
61 to 63 Spare 3
The Write Block ID is an index value used to determine the location in the
module’s database where the data will be placed. Each transfer can move up to
60 words (block offsets 1 to 60) of data.
Block Response from the Module to the Processor
These blocks of data transfer information from the module to the PLC processor.
The following table describes the structure of the input image.
Offset Description Length
0 Read Block ID 1
1 Write Block ID 1
2 to 61 Read Data 60
62 to 63 Spare 2
The Read Block ID is an index value used to determine the location of where the
data will be placed in the PLC processor user data table. Each transfer can move
up to 60 words (block offsets 2 to 61) of data.
The Write Block ID associated with the block requests data from the PLC
processor. Under normal program operation, the module sequentially sends read
blocks and requests write blocks. For example, if the application uses three read
and two write blocks, the sequence will be as follows:
R1W1

R2W2

R3W1

R1W2

R2W1

R3W2

R1W1

This sequence will continue until interrupted by other write block numbers sent by
the controller or by a command request from a node on the foreign network or
operator control through the mo
dule’s Configuration/Debug port.
If the ladder logic does not send a BTW instruction to the module quickly enough,
it is possible for the MVI71-ADM module to send a new BTR instruction
requesting the same write block ID.