Texas Instruments TMS320C645X - Manual (Page 143)

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5.42 LSUn Control Register 1 (LSUn_REG1)
SRIO Registers
There are four of these registers, one for each LSU.
Figure 98. LSUn Control Register 1 (LSUn_REG1)
31-16
ADDRESS_LSB_CONFIG_OFFSET
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
ADDRESS_LSB_CONFIG_OFFSET
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 72. LSUn Control Register 1 (LSUn_REG1) Field Descriptions
Bit Field Value Description
31-0 ADDRESS_LSB_
1. 32b Address- Packet Types 2,5, and 6 (will be used in conjunction with BYTE_COUNT to
CONFIG_OFFSE
create 64b aligned RapidIO packet header address).
T
2. 24b Config-offset Field - Maintenance Packets Type 8 (will be used in conjunction with
BYTE_COUNT to create 64b aligned RapidIO packet header Config_offset). The 2 lsb of this
field must be zero since the smallest configuration access is 4B.
SPRU976 – March 2006 Serial RapidIO (SRIO) 143
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