Texas Instruments TMS320C645X User Manual
Page 54
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SRIO Functional Description
Essentially, instead of the 24-bit value representing the period of the response timer, the period is now
defined as P = (2^24 x 16)/F. This means the countdown timer frequency needs to be 44.7 – 89.5Mhz for
a 6 – 3 second response timeout. Since the needed timer frequency is derived from the DMA bus clock
(which is device dependent), the hardware supports a programmable configuration register field to
properly scale the clock frequency. This configuration register field is described in the Peripheral Control
Register (Address offset 0x0004).
The CPU initiates a TX queue teardown by writing to the TX Queue Teardown command register.
Teardown of a TX queue will cause the following actions:
•
No new messages will be sent
•
All messages (single and multi-segment) already started will be completed
–
Failing to complete the message TX would leave an active receiver blocked waiting for the final
segments until the transaction eventually times-out.
–
Note that normal Tx SM operation is to not send any more segments once an error response has
been received on any segment. So if the receiver has been torn-down (and is receiving error
responses) multi-segment transmit will complete as soon as all in-transit segments have been
responded to.
•
When all in-transit messages/segments have been responded to, teardown will be completed as
follows:
–
If the queue is active, the teardown bit will be set in the next buffer descriptor in the queue. The
peripheral completes the teardown procedure by clearing the HDP register, setting the CP register
to 0xfffffffC, and issuing an interrupt for the given queue. The teardown command register bit is
automatically cleared by the peripheral.
–
If the queue is in-active (no additional buffer descriptors available), or becomes inactive after a
message in transmission is completed, no buffer descriptor fields are written. The HDP register and
the CP register remain unchanged. An interrupt is not issued. The teardown command register bit
is automatically cleared by the peripheral.
–
Because of topology differences between flow's response, packets may arrive in a different order to
the order of requests.
After the teardown process is complete and the interrupt is serviced by the CPU, software must
re-initialize the TX queue to restart normal operation.
2.3.4.3
Detailed Data Path Description
The CPPI module is the message passing protocol engine of the RapidIO peripheral. Messages contain
application specific data that is pushed to the receiving device comparable to a streaming write. Messages
do not contain read operations, but do have response packets.
The data path for this module uses the DMA bus as the DMA interface. The ftype header field of the
received RapidIO message packets are decoded by the logical layer of the peripheral. Only Type 11 and
Type 13 (transaction type1) packets are routed to this module. Data is routed from the priority based RX
FIFOs to the CPPI module’s data buffer within the shared buffer pool. The mbox header fields are
examined by the MailBox Mapper block of the CPPI module. Based on the mailbox, and message length,
the data is assigned memory addresses within memory. Data is transferred via DMA bus commands to
memory from the buffer space of the peripheral. The maximum buffer space should accommodate 256B of
data, as that is the maximum payload size of a RapidIO packet. Each message in memory will be
represented by a buffer descriptor in the queue.
2.3.4.4
Reset and Power Down State
Upon reset, the CPPI module must be configured by the CPU. The CPU sets up the receive and transmit
queues in memory. Then the CPU updates the CPPI module with the appropriate Rx/TX DMA state head
descriptor pointer, so the peripheral knows with which buffer descriptor address to start. Additionally, the
CPU must provide the CPPI module with initial buffer descriptor values for each data buffer. This step is
described more extensively in
of the CPPI specification.
54
Serial RapidIO (SRIO)
SPRU976 – March 2006