Texas Instruments TMS320C645X - Manual (Page 150)

www.ti.com
5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP)
SRIO Registers
There are sixteen of these registers.
Figure 105. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP)
31-16
TX_HDP
RW-0x00
LEGEND: R = Read only; -n = value after reset
15-0
TX_HDP
RW-0x00
LEGEND: R = Read only; -n = value after reset
Table 79. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) Field
Descriptions
Bit Field Value Description
31-0 TX_HDP This field is the host memory address for the first buffer descriptor in the transmit queue. This field
is written by the host to initiate queue transmit operations and is zeroed by the port when all
packets in the queue have been transmitted. An error condition results if the host writes this field
when the current field value is nonzero. The address must be 32-bit word aligned .
Serial RapidIO (SRIO) 150 SPRU976 – March 2006
Submit Documentation Feedback