Texas Instruments TMS320C645X - Manual (Page 63)

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A0 A0 A2 A2 A1 A1 A3 A3 L2 offset 0x0 DSP defined MMR
offset 0x1000
Byte
lane 0
31
Byte
lane 3
DMA 32b
0
SRIO Functional Description
2.3.8 Endianness
RapidIO is based on big endian. This is discussed in detail in section 2.4 of the RapidIO Interconnect
specification. Essentially, big endian specifies the address ordering as the most significant bit/byte first.
For example, in the 29-bit address field of a RapidIO packet (shown in
Figure 6 ) the left-most bit that is
transmitted first in the serial bit stream is the MSB of the address. Likewise, the data payload of the packet
is double-word aligned big-endian, which means the MSB is transmitted first. Bit 0 of all the
RapidIO-defined MMR registers is the MSB.
All endian specific conversion is handled within the peripheral. For double-word aligned payloads, the data
should be written contiguously into memory beginning at the specified address. Any unaligned payloads
will be padded and properly aligned within the 8-byte boundary. In this case, WDPTR, RDSIZE, and
WRSIZE RapidIO header fields indicate the byte position of the data within the double-word boundary. An
example of an unaligned transfer is shown in section 2.4 of the RapidIO Interconnect Specification.
There are no endian translation requirements for accessing the local MMR space. Regardless of the
device memory endian configuration, all configuration bus accesses are performed on 32-bit values at a
fixed address position. The bit positions in the 32-bit word are defined by this specification. This means
that a memory image which will be copied to a MMR is identical between little endian and big endian
configurations. Configuration bus reads are performed in the same manner.
Figure 29 illustrates the
concept. The desired operation is to locally update a serial RapidIO MMR (offset 0x1000) with a value of
0xA0A1A2A3, using the configuration bus.
Figure 29. Configuration Bus Example
When accessing RapidIO defined MMR within an external device, RapidIO allows 4B, 8B, or any multiple
of a double word access (up to 64B) for Type 8 Maintenance packets. The peripheral only supports 4B
accesses as the target, but can generate all sizes of request packets. RapidIO is defined as big endian
only, and has double-word aligned big endian packet payloads. The DMA, however, supports byte wide
accesses. The peripheral performs endian conversion on the payload if little endian is used on the device.
This conversion is not only applicable for Type 8 packets, but is also relevant for all outgoing payloads of
NWRITE, NWRITE_R, SWRITE, NREAD, and Message packets. This means that the memory image is
different between little endian and big endian configurations, as shown in
Figure 30 .
SPRU976 – March 2006 Serial RapidIO (SRIO) 63
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