Texas Instruments TMS320C645X - Manual (Page 32)

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Configuration/Status
Register and Tables
(32-bit)
Output Buffers
(64-bit)
RapidIO Endpoint
IT Generator
ASIC
Device
RapidIO Endpoint
L2
CPU
Step 2. IT to CPU
for end transfer
completion
Step 1. ASIC
writes through
RapidIO to L2
SRIO Functional Description
2.3.2.4 SERDES Configuration Example
rdata = SRIO_REGS->SERDES_CFG0_CNTL;
wdata = 0x00000001;
mask = 0x00000FFF;
mdata = (wdata & mask) | (rdata & ~mask);
SRIO_REGS->SERDES_CFG0_CNTL = mdata ; // 3.125 Gbps
SRIO_REGS->SERDES_CFG1_CNTL = mdata ; // 3.125 Gbps
SRIO_REGS->SERDES_CFG2_CNTL = mdata ; // 3.125 Gbps
SRIO_REGS->SERDES_CFG3_CNTL = mdata ; // 3.125 Gbps
SRIO_REGS->SERDES_CFGRX0_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX1_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX2_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGRX3_CNTL = 0x00081101 ; // enable rx, rate 1
SRIO_REGS->SERDES_CFGTX0_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX1_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX2_CNTL = 0x00010801 ; // enable tx, rate 1
SRIO_REGS->SERDES_CFGTX3_CNTL = 0x00010801 ; // enable tx, rate 1
2.3.3 DirectIO
The DirectIO (Load/Store) module serves as the source of all outgoing direct I/O packets. With Direct I/O,
the RapidIO packet contains the specific address where the data should be stored or read in the
destination device. Direct I/O requires that a RapidIO source device, must keep a local table of addresses
for memory within the destination device. If a CR ASIC is talking with DSP, the ASIC will have destination
circular buffer description tables that contain DSP addresses, buffer sizes, and write pointer information.
These tables are initialized by the DSP upon system boot after the initialization/discovery phase. Updates
to the table could be managed completely by the DSP through RapidIO master writes. Once these tables
are established, the ASIC RapidIO controller uses this data to compute the destination address and insert
it into the packet header. The DSP RapidIO peripheral extracts the destination address from the packet
header and transfers the payload to L2 memory via the DMA.
When a CPU wants to send data from memory to an external processing element (PE) or read data from
an external PE, it must provide the RIO peripheral vital information about the transfer such as DSP
memory address, target deviceID, target destination address, packet priority, etc. Essentially, a means
must exist to fill all the header fields of the RapidIO packet. The Load/Store module provides a mechanism
to handle this information exchange via a set of MMRs acting as transfer descriptors. These registers are
addressable by the CPU through the configuration bus. Upon completion of a write to LSU_Reg5, a data
transfer is initiated for either an NREAD, NWRITE, NWRITE_R, SWRITE, ATOMIC, or MAINTENANCE
RapidIO transaction. Some fields, such as the RapidIO srcTID/targetTID field, are assigned by hardware
and do not have a corresponding command register field.
Figure 9. Load/Store Data Transfer Diagram
32 Serial RapidIO (SRIO) SPRU976 – March 2006
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