Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 107)

Ethernet AVB Endpoint User Guide www.xilinx.com 107
UG492 September 21, 2010
Required Constraints
INST "*top/avb_configuration_inst/vlan_priority_a_int*" TNM = FFS
"vlan_priority_a";
INST "*top/rx_splitter_inst/vlan_priority_a_sample*" TNM = FFS
"vlan_priority_a_sample";
TIMESPEC "ts_vlan_priority_a_sample" = FROM "vlan_priority_a" TO
"vlan_priority_a_sample" TIG;
INST "*top/avb_configuration_inst/vlan_priority_b_int*" TNM = FFS
"vlan_priority_b";
INST "*top/rx_splitter_inst/vlan_priority_b_sample*" TNM = FFS
"vlan_priority_b_sample";
TIMESPEC "ts_vlan_priority_b_sample" = FROM "vlan_priority_b" TO
"vlan_priority_b_sample" TIG;
# clock domain crossing constraints for Tx Configuration
#---------------------------------------------------------
INST "*top/avb_configuration_inst/tx_cpu_reclock/wr_toggle"
TNM = FFS "tx_wr_toggle";
INST
"*top/avb_configuration_inst/tx_cpu_reclock/resync_write_toggle/data_s
ync" TNM = FFS "resync_tx_write_toggle";
TIMESPEC "ts_tx_wr_toggle" = FROM "tx_wr_toggle" TO
"resync_tx_write_toggle" TIG;
INST "*top/avb_configuration_inst/tx_cpu_reclock/rd_toggle"
TNM = FFS "tx_rd_toggle";
INST
"*top/avb_configuration_inst/tx_cpu_reclock/resync_read_toggle/data_sy
nc" TNM = FFS "resync_tx_read_toggle";
TIMESPEC "ts_tx_rd_toggle" = FROM "tx_rd_toggle" TO
"resync_tx_read_toggle" TIG;
INST "*top/avb_configuration_inst/tx_cpu_reclock/new_rd_toggle" TNM =
FFS "cpu_tx_rd_toggle";
INST
"*top/avb_configuration_inst/tx_cpu_reclock/resync_new_rd_toggle/data_
sync" TNM = FFS "resync_cpu_tx_rd_toggle";
TIMESPEC "ts_cpu_tx_rd_toggle" = FROM "cpu_tx_rd_toggle" TO
"resync_cpu_tx_rd_toggle" TIG;
INST "*top/avb_configuration_inst/tx_cpu_reclock/new_wr_toggle" TNM =
FFS "cpu_tx_wr_toggle";
INST
"*top/avb_configuration_inst/tx_cpu_reclock/resync_new_wr_toggle/data_
sync" TNM = FFS "resync_cpu_tx_wr_toggle";
TIMESPEC "ts_cpu_tx_wr_toggle" = FROM "cpu_tx_wr_toggle" TO
"resync_cpu_tx_wr_toggle" TIG;
INST "*top/avb_configuration_inst/tx_cpu_reclock/new_be*" TNM = FFS
"tx_cpu_sample";
INST "*top/avb_configuration_inst/tx_cpu_reclock/new_addr*" TNM = FFS
"tx_cpu_sample";
TIMESPEC "ts_tx_cpu_sample" = FROM "cpu_bus" TO "tx_cpu_sample" 16 ns
DATAPATHONLY;
INST "*top/avb_configuration_inst/clear_tx_int" TNM = FFS
"tx_regs_sample";