Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 111)

Ethernet AVB Endpoint User Guide www.xilinx.com 111
UG492 September 21, 2010
Chapter 12
System Integration
As described in Chapter 4, “Generating the Core” and Chapter 5, “Core Architecture” , the
core can be generated in one of two formats:
• “Standard CORE Generator Format”
This option will deliver the core in the standard CORE Generator™ output format, as
used by many other cores including previous versions of this core and all other
Ethernet LogiCORE™ IP solutions.
When generated in this format, the core is designed to interface to the LogiCORE IP
Tri-Mode Ethernet MAC or the LogiCORE IP Embedded Tri-Mode Ethernet MAC
wrappers. Refer to
“Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs” section
of this chapter.
• “EDK pcore Format”
This option will deliver the core in the standard pcore format, suitable for directly
importing into the Xilinx Embedded Development Kit (EDK) environment.
When generated in this format, the core is designed to interface to the XPS LocalLink
Tri-Mode Ethernet MAC (xps_ll_temac). Refer to
“Using the Xilinx XPS LocalLink Tri-
Mode Ethernet MAC” section of this chapter.
• The Ethernet AVB hardware can also be generated as part of the AXI_Ethernet
LogiCORE by setting the AXI_Ethernet parameter C_AVB=1. See the
“Using the Xilinx
AXI Ethernet MAC” section of this chapter.
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
The Ethernet AVB Endpoint core should be generated in the “Standard CORE Generator
Format” .
The Ethernet AVB Endpoint core can be connected to the following Ethernet MACs from
the CORE Generator LogiCORE IP library:
• “LogiCORE IP Tri-Mode Ethernet MAC (Soft Core)” , available for all Spartan®-3,
Spartan-3E, Spartan-3A, Spartan-3A DSP, Spartan-6, Virtex®-5 and Virtex-6 devices.
• “LogiCORE IP Embedded Tri-Mode Ethernet MACs” , available in selected Virtex-5
and Virtex-6 devices.
Please also refer to individual product documentation.