Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 117)

Ethernet AVB Endpoint User Guide www.xilinx.com 117
UG492 September 21, 2010
Using the Xilinx LogiCORE IP Tri-Mode Ethernet MACs
Connections Without Ethernet Statistics
Figure 12-3 illustrates the connection of the Ethernet AVB Endpoint core to the Xilinx Tri-
Mode Ethernet MAC (EMAC) core when not using the Ethernet Statistics core. Figure 12-3
provides detail for the connections between the two cores which were shown in Figure 5-1 .
All connections, as shown, are logic-less connections. Because the AVB standard does not
include support for half-duplex or flow control operation, the relevant half-duplex/flow-
control signals of the EMAC can be left unused: inputs can be tied to logic 0, outputs can be
left unconnected.
X-Ref Target - Figure 12-3
Figure 12-3: Connection to the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC
(without Ethernet Statistics)
tx_clk
tx_clk_en
tx_data[7:0]
rx_clk
rx_clk_en
rx_data[7:0]
rx_data_valid
rx_frame_good
rx_frame_bad
host_opcode[1:0]
host_addr[9:0]
host_wr_data[31:0]
host_req
host_miim_sel
host_miim_rdy
host_rd_data_mac[31:0]
host_rd_data_stats[31:0]
host_stats_lsw_rdy
host_stats_msw_rdy
host_clk
CLIENTEMAC0PAUSEREQ
CLIENTEMAC0PAUSEVAL[15:0]
TX_CLK_0
TX_CLIENT_CLK_ENABLE_0
CLIENTEMAC0TXD[7:0]
CLIENTEMAC0TXDVLD
CLIENTEMAC0TXUNDERRUN
EMAC0CLIENTTXACK
EMAC0CLIENTTXCOLLISION
EMAC0CLIENTTXRETRANSMIT
CLIENTEMAC0IFGDELAY
GMII_RX_CLK0
RX_CLIENT_CLK_ENABLE_0
EMAC0CLIENTRXD[7:0]
EMAC0CLIENTRXDVLD
EMAC0CLIENTRXGOODFRAME
EMAC0CLIENTRXBADFRAME
HOSTADDR[9:0]
HOSTWRDATA[31:0]
HOSTREQ
HOSTMIIMSEL
HOSTMIIMRDY
HOSTRDDATA[31:0]
HOSTCLK
HOSTEMAC1SEL
EMAC0CLIENTTXSTATS
EMAC0CLIENTTXSTATSVLD
EMAC0CLIENTTXSTATSBYTEVLD
EMAC0CLIENTRXSTATS[6:0]
EMAC0CLIENTRXSTATSVLD
EMAC0CLIENTRXSTATSBYTEVLD
host_clk
NC
NC
NC
NC
GND
GND
GND
NC
NC
NC
NC
NC
GND
tx_data_valid
tx_underrun
tx_ack
Ethernet AVB Endpoint
Core Netlist
Block-level Wrapper
(from Virtex-5 Embedded Tri-mode
Ethernet MAC Wrapper)
HOSTOPCODE[1:0]