Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual
Page 45
Ethernet AVB Endpoint User Guide
45
UG492 September 21, 2010
Functional Block Description
RTC
A significant component of the PTP network wide timing synchronization mechanism is
the Real Time Counter (RTC), which provides the common time of the network. Every
device on the network will maintain its own local version.
The RTC is effectively a large counter which consists of a 32-bit nanosecond field (the unit
of this field is 1 nanosecond and this field will count the duration of exactly one second,
then reset back to zero) and a 48-bit second field (the unit of this field is one second: this
field will increment when the nanosecond field saturates at 1 second). The seconds field
will only wrap around when its count fully saturates. The entire RTC is therefore designed
never to wrap around in our lifetime. The RTC counter is implemented as part of the core
in hardware.
Conceptually, this counter is not related to the frequency of the clock used to increment it.
A configuration register within the core provides a configurable increment rate for this
counter; this increment register simply takes the value of the clock period which is being
used to increment the RTC. However, the resolution of this increment register is very fine,
in units of 1/1048576 (1/2
20
) fraction of one nanosecond. For this reason, the RTC
increment rate can be adjusted to a very fine degree of accuracy. This provides the
following features:
•
The RTC can be incremented from any available clock frequency that is greater than
the AVB standards defined minimum of 25 MHz. However, the faster the frequency of
the clock, the smaller will be the step increment and the smoother will be the overall
RTC increment rate. Xilinx recommends clocking the RTC logic at 125 MHz because
this is a readily available clock source (obtained from the transmit clock source of the
Ethernet MAC at 1 Gbps speed). This frequency significantly exceeds the minimum
performance of the P802.1AS specification.
•
When acting as a clock slave, the rate adjustment of the RTC can be matched to that of
the network clock master to an exceptional level of accuracy. The software drivers
provided with this core will periodically calculate the increment rate error between
itself and the master and update the RTC increment value accordingly.
The core also contains a configuration register which allows a large step change to be made
to the RTC. This can be used to initialize the RTC, after power-up. It is also used to make
periodic corrections, as required, by the software drivers when operating as a clock slave;
if the increment rates are closely matched, these periodic step corrections will be small. See
Chapter 9, “Precise Timing Protocol Packet Buffers”
for further information.