Rainbow Electronics MAX16066 - Manual (Page 37)

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
MAX16065/MAX16066
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The normal watchdog timeout period, t WDI , begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, t
WDI_STARTUP (Figures 7
and 8). During the normal operating mode, WDO asserts
if the FP does not toggle WDI with a valid transition
(high-to-low or low-to-high) within the standard timeout
period, t
WDI . WDO remains asserted until WDI is toggled
or RESET is asserted (Figure 9).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until the power-
on mode is reached and RESET is deasserted. The
watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 10). The watchdog timer will
be held in reset while RESET is asserted.
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, t
RP , when the watchdog timer expires
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1Fs) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1.’ A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 24 for more
information on configuring watchdog functionality.
Figure 8. Normal Watchdog Startup Sequence
Figure 9. Watchdog Timer Operation
LAST MON_
WDI
V
TH
t WDI_STARTUP
< t
WDI
t
RP
RESET
< t WDI
WDI
WDO
0V
V CC
0V
V CC
< t
WDI
< t
WDI < t WDI < t WDI
> t
WDI
< t
WDI
< t
WDI
t
WDI