Rainbow Electronics AT89C51SND1C - Manual (Page 108)

108
AT8xC51SND1C
4109E–8051–06/03
Table 103. UFNUMH Register
UFNUMH (S:BBh, Read-only) – USB Frame Number High Register
Reset Value = 00h
Table 104. USBCLK Register
USBCLK (S:EAh) – USB Clock Divider Register
Reset Value = 0000 0000b
7 6 5 4 3 2 1 0
- - CRCOK CRCERR - FNUM10 FNUM9 FNUM8
Bit
Number
Bit
Mnemonic Description
7 - 3 -
Reserved
The value read from these bits is always 0. Do not set these bits.
5 CRCOK
Frame Number CRC OK Bit
Set by hardware after a non corrupted Frame Number in Start of Frame Packet is
received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
4 CRCERR
Frame Number CRC Error Bit
Set by hardware after a corrupted Frame Number in Start of Frame Packet is
received.
Updated after every Start Of Frame packet reception.
Note: The Start Of Frame interrupt is generated just after the PID receipt.
3 -
Reserved
The value read from this bits is always 0. Do not set this bit.
2-0 FNUM10:8
Frame Number
Upper 3 bits of the 11-bit Frame Number. It is provided in the last received SOF
packet. FNUM does not change if a corrupted SOF is received.
7 6 5 4 3 2 1 0
- - - - - - USBCD1 USBCD0
Bit
Number
Bit
Mnemonic Description
7 - 2 -
Reserved
The value read from these bits is always 0. Do not set these bits.
1 - 0 USBCD1:0
USB Controller Clock Divider
2-bit divider for USB controller clock generation.