Table 120, Table 119), At8xc51snd1c – Rainbow Electronics AT89C51SND1C User Manual
Page 130
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130
AT8xC51SND1C
4109E–8051–06/03
Table 119. MMDAT Register
MMDAT (S:DCh) – MMC Data Register
Reset Value = 1111 1111b
Table 120. MMCLK Register
MMCLK (S:EDh) – MMC Clock Divider Register
Reset Value = 0000 0000b
7
6
5
4
3
2
1
0
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
Bit
Number
Bit
Mnemonic
Description
7 - 0
MD7:0
MMC Data Byte
Input (write) or output (read) register of the data FIFO.
7
6
5
4
3
2
1
0
MMCD7
MMCD6
MMCD5
MMCD4
MMCD3
MMCD2
MMCD1
MMCD0
Bit
Number
Bit
Mnemonic
Description
7 - 0
MMCD7:0
MMC Clock Divider
8-bit divider for MMC clock generation.
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