Rainbow Electronics AT89C51SND1C - Manual (Page 63)

63
AT8xC51SND1C
4109E–8051–06/03
MP3 Data The MP3 decoder does not start any frame decoding before having a complete frame in
its input buffer
(1) . In order to manage the load of MP3 data in the frame buffer, a hard-
ware handshake consisting of data request and data acknowledgment is implemented.
Each time the MP3 decoder needs MP3 data, it sets the MPREQ, MPFREQ and
MPBREQ flags respectively in MP3STA and MP3STA1 registers. MPREQ flag can gen-
erate an interrupt if enabled as explained in Section “Interrupt”. The CPU must then load
data in the buffer by writing it through MP3DAT register thus acknowledging the previ-
ous request. As shown in Figure 43, the MPFREQ flag remains set while data (i.e a
frame) is requested by the decoder. It is cleared when no more data is requested and
set again when new data are requested. MPBREQ flag toggles at every Byte writing.
Note: 1. The first request after enable, consists in 1024 Bytes of data to fill in the input buffer.
Figure 43. Data Timing Diagram
MP3 Clock The MP3 decoder clock is generated by division of the PLL clock. The division factor is
given by MPCD4:0 bits in MP3CLK register. Figure 44 shows the MP3 decoder clock
generator and its calculation formula. The MP3 decoder clock frequency depends only
on the incoming MP3 frames.
Figure 44. MP3 Clock Generator and Symbol
As soon as the frame header has been decoded and the MPEG version extracted, the
minimum MP3 input frequency must be programmed according to Table 68.
Table 68. MP3 Clock Frequency
MPFREQ Flag
MPBREQ Flag
MPREQ Flag Cleared when Reading MP3STA
Write to MP3DAT
MPEG Version Minimum MP3 Clock (MHz)
I 21
II 10.5
MPCD4:0
MP3CLK
MP3 Decoder Clock
MP3clk
PLL clk
MPCD 1 +
---------------------------- =
MP3
CLOCK
MP3 Clock Symbol
PLL
CLOCK