Rainbow Electronics AT89C51SND1C - Manual (Page 148)

148
AT8xC51SND1C
4109E–8051–06/03
Slave Mode The SPI operates in slave mode when the MSTR bit in SPCON is cleared and data has
been loaded in SPDAT.
Figure 114 shows the SPI block diagram in slave mode. In slave mode, before a data
transmission occurs, the SS pin of the slave SPI must be asserted to low level. SS must
remain low until the transmission of the Byte is complete. In the slave SPI module, data
enters the shift register through the MOSI pin under the control of the serial clock pro-
vided by the master SPI module on the SCK input pin. When the master starts a
transmission, the data in the shift register begins shifting out on the MISO pin. The end
of transfer is signaled by SPIF being set.
When the AT8xC51SND1C is the only slave on the bus, it can be useful not to use SS#
pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON.
This bit has no effect when CPHA is cleared (see Section "SS Management",
page 150).
Figure 114. SPI Slave Mode Block Diagram
Note: 1. MSTR bit in SPCON is cleared to select slave mode.
Bit Rate The bit rate can be selected from seven predefined bit rates using the SPR2, SPR1 and
SPR0 control bits in SPCON according to Table 131. These bit rates are derived from
the peripheral clock (F
PER
) issued from the Clock Controller block as detailed in Section
"Oscillator", page 12.
MISO/P4.2
MOSI/P4.1
SS/P4.3 SPIF
SPSTA.7
CPOL
SPCON.3
CPHA
SPCON.2
8-bit Shift Register
SPDAT WR
I Q
In
te
rnal Bus
SPDAT RD
SCK/P4.2
SSDIS
SPCON.5
Control and Clock Logic