Achronix Speedster22i DDR - Manual (Page 10)

enabled, the SIZE parameters and consequently the bus width,
are doubled.
ddr_int_rd_request 1 Input Read request.
ddr_int_rddata
[SIZE*4-
1:0]
Output
Data read back from the DDR Memory in response to a read
request. SIZE: 72, 64, 32, 16, 8. When the wide bus interface is
enabled, the SIZE parameters and consequently the bus width,
are doubled.
ddr_int_rddata_valid 9 Output Valid signal corresponding to read data (‘ddr_int_rddata’).
ddr_int_rddata_valid_early 9 Output
Early valid signal corresponding to read data
(‘ddr_int_rddata’)
ddr_int_rddata_valid_align 9 Output
When the wide bus interface is enabled and in 2X clock mode,
valid signal corresponding to read data (‘ddr_int_rddata’)
ddr_int_rddata_valid_early_align 9 Output
When the wide bus interface is enabled and in 2X clock mode,
early valid signal corresponding to read data
(‘ddr_int_rddata’)
ddr_int_cmd_auto_pch 1 Input Core can send a Auto pre charge request to controller
ddr_int_cmd_power_down 2 Input
Core can send a power down request to controller. Each signal
[1:0] controls each SDRAM on its chip select.
ddr_int_cmd_ref_req 1 Input
User-initiated refresh control. Core can send a refresh request
to controller (manual control).
ddr_int_ref_ack 1 Output Refresh acknowledgement from controller to core
ddr_int_cmd_self_referesh 2 Input
Self refresh control. Causes the DDR3 SDRAM Controller Core
to put the SDRAM into self refresh mode at the next refresh
event. Each signal [1:0] controls each SDRAM on its chip
select.
ddr_int_cmd_zq_cal_req 2 Input
User initialized ZQ calibration. User can initiate ZQ calibration
at next available opportunity. Each signal [1:0] controls each
SDRAM on its chip select.
ddr_int_zq_cal_ack 1 Output
ZQ calibrations acknowledge. Asserted for one clock when ZQ
calibration command is issued to memory devices.
ddr_int_wrdata_valid 1 Output
Frames the active data being written to SDRAM. Mimics
‘ddr_int_wrdata_req’ except it is delayed by one clock.
ddr_int_phy_ci_slave_adj 8 input
ddr_int_phy_ci_slave_dqsn_en 9 Input *based on data width
ddr_int_phy_co_wr_lvl_out 9 Output *based on data width
ddr_int_init_ack 1 Output
Asserts for one clock to acknowledge init_refresh,
init_precharge_all, init_mr, init_zq_cal, and
init_wlvl_mrX_req. **
ddr_int_init_wlvl_done 1 Output Indicates completion of write leveling
status_wlvl_tap_value 9 Output
Delay line value determined by write leveling calibration
inside DDR3 controller. The value on this port corresponds to
the DQS lane selected by ‘**’ parameter **
wlvl_active 1 Output
Indicates that controller-driven automatic write leveling is in
progress.
Table-1: Internal interface signals
10 UG031, Nov 18, 2014