Achronix Speedster22i DDR - Manual (Page 23)

As shown above, the wrdata_req signal needs to be asserted for one clock cycle, and in the
subsequent clock cycle the write data [575:0] is provided. The timing relationships with the
SDRAM interface are essentially equivalent to the 2X Clock Mode interface.
A valid write request (ie. one which is successfully posted to the Speedster22i DDR Controller
and propagated to the DDR Memory) is one in which ALL of the following conditions are
met:
• ‘ddr_int_wr_request’ is asserted (active high)
• ‘ddr_int_addr [33:0]’ is driven
• ‘ddr_int_burst_size [7:0]’ is driven to a valid value for the given protocol
o
8’d4  8’d252 for DDR3 (multiple of 4)
• ‘ddr_int_busy_align’ is not asserted (active high)
• Latency of the DDR-controller provided data (ddr_int_wrdata) to the external
memory is 8-cycle.
Read Interface Details
The Speedster22i DDR Controller contains a very simple read interface to the DDR Driver
logic.
2X Clock mode must always be used. When using 2X clock mode DDR drive (user) logic in
core runs at half the frequency of DDR controller. The DDR controller/PHY outputs a Clock
(‘clk_div2’), which the user must use to drive write data and latch read data.
The core interface signals remain the same except for (‘ddr_int_busy’, ddr_int_wrdata_req’,
’ddr_int_wrdata_req_early’, ‘ddr_int_rddata_valid’, ‘ddr_int_rddata_valid_early’). Instead,
the DDR driver (user) logic needs to use (‘ddr_int_busy_align’, ‘ddr_int_wrdata_req_align’,
’ddr_int_wrdata_req_early_align’, ‘ddr_int_rddata_valid_align’,
‘ddr_int_rddata_valid_early_align’).
The DDR driver (user) logic must provide a read request (‘ddr_int_rd_request’) along with a
corresponding address (‘ddr_int_addr’) and burst length (‘ddr_int_burst_size’).
Speedster22i DDR controller provides valid signal for data to be read. This valid signal is
‘ddr_int_rddata_valid_align’. After assertion of ‘ddr_int_rddata_valid_align’, 2 cycles later,
the DDR driver logic receives read data (‘ddr_int_rddata [287:0]’) from the Speedster22i DDR
controller. The ‘ddr_int_rddata [287:0]’ signal represents the data read from the memory over
four sequential DDR clock edges (72 bits at a time). The data contained in ‘ddr_int_rddata
[71:0]’ is read from the specified column address, and that contained in ‘ddr_int_rddata
[143:72]’ is read from the specified column address + 1. Data from ‘ddr_int_rddata [215:144]’
is read from specified column address+2 and data from ‘ddr_int_rddata [287:216]’ is read
from specified column address+3.
The read requests are subject to the controller being busy (‘ddr_int_busy_align’).
The DDR controller supports burst length option BL8. Each burst will contain 2 local side
transfers, which is equivalent to 8 transfers to the DDR memory.
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