Achronix Speedster22i DDR - Manual (Page 17)

ddr_int_ wrdata_req_ early_ align
Clk_div2
ddr_int_wr_ request
a0 ddr_int_ addr[33:0]
ddr_int_ busy_ align
ddr_int_ wrdata_req
ddr_int_ wrdata[ 287:0]
Valid Write commands
ddr_int_ burst_size[7:0]
4
d0 d1
Timing relationship between ddr_int_wr_request assertion and
ddr_int_wrdata_req assertion between AL/CWL configurations settings/refresh
status, and status of bank/row being accessed
Present data 1 cycle after
ddr_int_wrdata_req_early_align is asserted
Figure 6: Internal Interface Write Protocol Timing Diagram with default value ‘addrcmd_delay’ to 8
This logic then needs to provide data (‘ddr_int_wrdata’) 1 clock cycles after a data request
(‘ddr_int_wrdata_req_early_align’) is received from the Speedster22i DDR Controller. The
logic can also use (‘ddr_int_wrdata_req_align’). The ‘ddr_int_wrdata [287:0]’ signal
represents the data to be written to the memory over four sequential DDR clock edges (72
bits at a time). The data contained in ‘ddr_int_wrdata [71:0]’ is written to the specified
column address, and that contained in ‘ddr_int_wrdata [143:72]’ is written to the specified
column address + 1. Data from ‘ddr_int_wrdata [215:144]’ will be written to specified column
address+2 and data from ‘ddr_int_wrdata [287:216]’ will be written to specified column
address+3.
The write requests are subject to the controller being busy (‘ddr_int_busy_align’).
The DDR controller supports burst length option BL8. Each burst will contain 2 local side
transfers, which is equivalent to 8 transfers to the DDR memory.
The diagram above shows the signals between the FPGA fabric core and DDR controller.
(‘ddr_int_wrdata_req_early_align’) signal is 3 cycles earlier then (‘ddr_int_wrdata_req’)
signal. The user can use ‘ddr_int_wrdata_req_early_align’ signal to be ready to write the data
and at the assertion of ‘ddr_int_wrdata_req’ signal to drive user data on ‘ddr_int_wrdata’.
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