Achronix Speedster22i DDR - Manual (Page 29)

To request a read data transaction, the DDR driver (user) logic must assert
‘ddr_int_rd_request’ along with a corresponding address (‘ddr_int_addr [33:0]’) and burst
length (‘ddr_int_burst_size’).
A valid read request (ie. one which is successfully posted to the Speedster22i DDR controller
and propagated to the DDR Memory) is one in which ALL of the following conditions are
met:
• ‘ddr_int_rd_request’ is asserted (active high)
• ‘ddr_int_addr [33:0]’ is driven
• ‘ddr_int_burst_size [7:0]’ is driven to a valid value for the given protocol
o
8’d4  8’d252 for DDR3 (multiple of 4)
o
‘ddr_int_busy_align’ is not asserted (active high)
UG031, Nov 18, 2014 29