Achronix Speedster22i DDR - Manual (Page 21)

column address provided by the user for the given write request. For DDR3, since
‘ddr_int_burst_size’ is set as a multiple of 4, the user should always provide a column
address with a modulo-8 value.
The ‘ddr_int_wrdata [287:0]’ signal represents the data to be written to the memory over two
sequential DDR clock edges (144 bits at a time). The data contained in ‘ddr_int_wrdata
[71:0]’ is written to the specified column address, that contained in ‘ddr_int_wrdata [143:72]’
is written to the specified column address + 1, that contained in ‘ddr_int_wrdata [215:144]’ is
written to the specified column address + 2, and that contained in ‘ddr_int_wrdata [287:216]’
is written to the specified column address + 3.
The ‘ddr_int_writedata_mask [17:0]’ represents the data mask. Each bit within this bus
corresponds to 8bits of the ‘ddr_int_wrdata [287:0]’ signal bus. Asserting a given bit within
the ‘ddr_int_writedata_mask’ bus ensures that the corresponding 8 bits of the
‘ddr_int_wrdata’ bus do NOT get written to memory, overwriting its previous contents.
Write Protocol with Wide Bus Interface Enabled
The DDR macro for Speedster22i Devices also provides users the option to ‘Enable a Wide
Bus Interface’ through a checkbox control. In this mode, the DDR driving logic (user RTL
implemented in the FPGA fabric) runs at one quarter the frequency of the DDR controller.
This enabled FPGA fabric core timing to be met more easily, especially for high off-chip data
rates. The DDR controller/PHY outputs a clock (‘clk_div4’), which the user must use to drive
write data and latch read data. With a 1866Mbps data rate at the DDR controller,
corresponding to the PHY operating at 1066MHz, enabling the wide bus interface ensures
that the interface in the fabric can operate at 266MHz. The wide bus interface can be enabled
for any and all modes and data rates.
When the wide bus interface is enabled, the core interface signals remain almost exactly the
same as those required in the 2X clock mode. The only differences are that a new clock
(‘clk_div4’) need be used, and the data and mask bus widths effectively double.
The DDR driver logic (user RTL) provides a write request (‘ddr_int_wr_request’) along with
a corresponding address (‘ddr_int_addr’) and burst length (‘ddr_int_burst_size’).
This logic then needs to provide data (‘ddr_int_wrdata’) 1 clock cycle after a data request
(‘ddr_int_wrdata_req_early_align’) is received from the Speedster22i DDR Controller. The
logic can also use (‘ddr_int_wrdata_req_align’). The ‘ddr_int_wrdata [575:0]’ signal
represents the data to be written to the memory over eight sequential DDR clock edges (72
bits at a time). The data contained in ‘ddr_int_wrdata [71:0]’ is written to the specified
column address, and that contained in ‘ddr_int_wrdata [143:72]’ is written to the specified
column address+1. Data from ‘ddr_int_wrdata [215:144]’ will be written to specified column
address+2 and data from ‘ddr_int_wrdata [287:216]’ will be written to specified column
address+3. Similarly, data contained in ‘ddr_int_wrdata [359:288]’ is written to the specified
column address+4, and that contained in ‘ddr_int_wrdata [431:360]’ is written to the specified
column address+5. Data from ‘ddr_int_wrdata [503:432]’ will be written to specified column
address+6 and data from ‘ddr_int_wrdata [575:504]’ will be written to specified column
address+7.
The write requests are subject to the controller being busy (‘ddr_int_busy_align’).
The DDR controller supports burst length option BL8. Each burst will contain a single local
side transfers, which is equivalent to 8 transfers to the DDR memory.
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