Achronix Speedster22i DDR - Manual (Page 15)

Write Interface Details
The Speedster22i DDR controller contains a simple write interface to the DDR Driver logic..
This uses a 2X clock mode - the DDR driving logic (user RTL implemented in the FPGA
fabric) runs at half the frequency of DDR controller. The DDR controller/PHY outputs a
Clock (‘clk_div2’), which the user must use to drive write data and latch read data. For
example, a 1866Mbps data rate required the DDR controller and PHY to operate at 1066MHz,
but the 2X mode allows the internal interface to the fabric to operate at 533MHz. If 2X mode
is not used, the highest off chip data rate available is 1066Mbps.
In 2X mode, the core interface signals remain the same except for (‘ddr_int_busy’,
ddr_int_wrdata_req’, ’ddr_int_wrdata_req_early’, ‘ddr_int_rddata_valid’,
‘ddr_int_rddata_valid_early’). Instead of the above signals, users must interface with the
following signals (‘ddr_int_busy_align’, ddr_int_wrdata_req_align’,
’ddr_int_wrdata_req_early_align’, ‘ddr_int_rddata_valid_align’,
‘ddr_int_rddata_valid_early_align’).
The DDR driver logic (user RTL) provides a write request (‘ddr_int_wr_request’) along with
a corresponding address (‘ddr_int_addr’) and burst length (‘ddr_int_burst_size’).
This logic then needs to provide data (‘ddr_int_wrdata’) 2 clock cycles after a data request
(‘ddr_int_wrdata_req_early_align’) is received from the Speedster22i DDR Controller. The
logic can also use (‘ddr_int_wrdata_req_align’). The ‘ddr_int_wrdata [287:0]’ signal
represents the data to be written to the memory over four sequential DDR clock edges (72
bits at a time). The data contained in ‘ddr_int_wrdata [71:0]’ is written to the specified
column address, and that contained in ‘ddr_int_wrdata [143:72]’ is written to the specified
column address + 1. Data from ‘ddr_int_wrdata [215:144]’ will be written to specified column
address+2 and data from ‘ddr_int_wrdata [287:216]’ will be written to specified column
address+3.
The write requests are subject to the controller being busy (‘ddr_int_busy_align’).
The DDR controller supports burst length option BL8. Each burst will contain 2 local side
transfers, which is equivalent to 8 transfers to the DDR memory.
Figure 4: Write Interface 2X Clock Mode
Speedster22i
DDR
Controller
DDR Interface
Logic
(User RTL)
ddr_int_wr_request
ddr_int_busy_align
ddr_int_addr[33:0]
ddr_int_wrdata_req_align
ddr_int_wrdata[287:0]
ddr_int_burst_size[7:0]
ddr_int_writedata_mask[17:0]
ddr_int_wrdata_req_early_align
Clk_div2
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