Achronix Speedster22i DDR - Manual (Page 25)

The Corresponding external (off-chip) interface timing signals are shown in the Figure 14
below.
Figure 14: External Interface Read Protocol Timing Diagram
To request a read data transaction, the DDR driver (user) logic must assert
‘ddr_int_rd_request’ along with a corresponding address (‘ddr_int_addr [33:0]’) and burst
length (‘ddr_int_burst_size’).
A valid read request (ie. one which is successfully posted to the Speedster22i DDR controller
and propagated to the DDR Memory) is one in which ALL of the following conditions are
met:
• ‘ddr_int_rd_request’ is asserted (active high)
• ‘ddr_int_addr [33:0]’ is driven
• ‘ddr_int_burst_size [7:0]’ is driven to a valid value for the given protocol
o
8’d4  8’d252 for DDR3 (multiple of 4)
• ‘ddr_int_busy_align’ is not asserted (active high)
Back-to-Back Read Protocol 2X Clock Mode
The 1 st word is provided on (‘ddr_int_rddata [143:0]’) 4 cycles after (‘ddr_int_rddata_valid’)
is received from the Speedster22i DDR controller.
The following timing diagrams illustrate two cascaded, back-to-back read commands. Each
valid read request (and corresponding data) is highlighted in a different color. The testing is
done with respect to 2X-clock mode.
clock
Command
sd_ras_n
sd_cas_n
Notes: For case shown, DELAY_ACTIVATE_TO_RW = 5, CAS LATENCY =7, DELAY_ADDITIVE_DDR3_LATENCY=0
d0r d0f d1r d1f d2r d2f d3r d3f
ACT RD
sd_we_n
sd_a
sd_ba
sd_cs_n
sd_dq
sd_dm
sd_dqs
ROW COL
BANK BANK
CHIP CHIP
UG031, Nov 18, 2014 25