Achronix Speedster22i DDR - Manual (Page 27)

trip delay of accessing as well as actually reading from the memory address. The read data is
accompanied by a valid signal, denoted ‘ddr_int_rddata_valid.’
The Speedster22i DDR Controller will ensure that the ‘ddr_int_rddata_valid’ signal is
asserted for the correct number of cycles (based on the ‘ddr_int_burst_size’ value specified
for the corresponding read request) as well as at the correct time (in accordance with DDR
latency requirements based on user-specified values of AL and CL parameters and the total
round-trip latency of the given memory access).
The burst length (‘ddr_int_burst_size’) corresponding to a single given read request must be
set to a valid value based on the given DDR protocol. For DDR3 has a range of 8’d4 to
8’d252. Note that the ‘ddr_int_burst_size’ value translates directly to the number of cycles
for which ‘ddr_int_rddata_valid’ is asserted.
As with writes, while bank and row addresses are derived directly from the address
provided by the DDR driver (user) logic for a given read request, the column address is
incremented automatically within the Speedster22i DDR Controller, starting with the column
address provided by the user. For DDR3, since ‘ddr_int_burst_size’ is set as a multiple of 4,
the user should always provide a column address with a modulo-8 value.
The ‘ddr_int_rddata [287:0]’ signal represents the data read from the memory over two
sequential DDR clock edges (144 bits at a time). The data contained in ‘ddr_int_rddata [71:0]’
is read from the specified column address, that contained in ‘ddr_int_rddata [143:72]’ is read
from the specified column address + 1, that contained in ‘ddr_int_rddata [215:144]’ is read
from the specified column address + 2, and that contained ‘ddr_int_rddata [287:216]’ is read
from the specified column address + 3.
Read Protocol with Wide Bus Interface Enabled
As mentioned earlier, the wide bus interface may be enabled for all data rates but is
particularly useful at high data rates to ease the timing closure effort for logic in the FPGA
fabric. When the wide bus interface is enabled, the DDR driver (user) logic in core runs at
one quarter the frequency of the DDR controller. The DDR controller/PHY outputs a clock
(‘clk_div4’), which the user must use to drive write data and latch read data.
The core interface signals are essentially exactly the same as those in 2X clock mode, except
that the data and mask bus widths are doubled and all signals are aligned to the new clock
(‘clk_div4’) provided by the DDR controller/PHY.
The DDR driver (user) logic must provide a read request (‘ddr_int_rd_request’) along with a
corresponding address (‘ddr_int_addr’) and burst length (‘ddr_int_burst_size’).
Speedster22i DDR controller provides valid signal for data to be read. This valid signal is
‘ddr_int_rddata_valid_align’. After assertion of ‘ddr_int_rddata_valid_align’, 2 cycles later,
the DDR driver logic receives read data (‘ddr_int_rddata [575:0]’) from the Speedster22i DDR
controller. The ‘ddr_int_rddata [575:0]’ signal represents the data read from the memory over
eight sequential DDR clock edges (72 bits at a time). The data contained in ‘ddr_int_rddata
[71:0]’ is read from the specified column address, and that contained in ‘ddr_int_rddata
[143:72]’ is read from the specified column address+1. Data from ‘ddr_int_rddata [215:144]’ is
read from specified column address+2 and data from ‘ddr_int_rddata [287:216]’ is read from
specified column address+3. Similarly, data contained in ‘ddr_int_rddata [359:288]’ is read
from the specified column address+4, and that contained in ‘ddr_int_rddata [431:360]’ is read
from the specified column address+5. Data from ‘ddr_int_rddata [503:432]’ is read from
specified column address+6 and data from ‘ddr_int_rddata [575:504]’ is read from specified
column address+7.
UG031, Nov 18, 2014 27