Kontron COMe-cP2020 - Manual (Page 33)

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COMe-P2020 User Guide
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2.5.2 Signal Descriptions COM Express Connectors
2.5.2.1 Ethernet (Group GigE MDI)
The COMe-cP2020 module provides three Gigabit Ethernet interface whose signals are already at copper Ethernet transmis-
sion voltage levels (physical levels / MDI) in accordance to the COM Express Base Specification. So the carrier board needs
to add only the galvanic isolation (magnetics) function and the appropriate transmission connector type.
Additionally, for monitoring and control purposes, LED functionality is provided to indicate activity (GBE[0..2]), Ethernet
link (GBE[0..2]_LINK#), Ethernet speed 100Mbit/s (GBE[0..2]_LINK100#) and Ethernet speed 1000Mbit/s
(GBE[0..2]_LINK1000#).
Reference voltage for carrier board Ethernet magnetics center tap is not required.
2.5.2.2 Ethernet Management (ETH MGT)
The management communication between the Ethernet MACs and the external connected Ethernet PHYs is realized by using
the signal group ETH MGT (EC_MDC, EC_MDIO).
2.5.2.3 IEEE 1588
The Freescale QorIQ CPUs provide support for the Ethernet Precision Time Protocol (PTP) defined in the IEEE 1588 specifica-
tion. In order to utilize this functionality the CPUs provide additional IEEE 1588 time stamp signals. For a more detailed
description of those signals please refer to the CPU’s reference manual.
2.5.2.4 SerDes
The signal group SerDes reflects all the high speed low voltage differential signals provided by the CPU. The SerDes signals
are grouped into so called lanes and links.
A set of differential signal pairs, one pair for transmission and one pair for reception is called a lane. One or more lanes
together form a link which can support various logical protocols such as: PCIe, sRIO, SGMII.
The P2020 Processor provides 4 SerDes lanes (lane #0 to lane #3). SerDes lanes #1 to #3 are configurable. Each lane can be
switched via on-board multiplexer to different COMe connector SerDes Ports. The multiplexer are controlled by CPLD, see
chapter
xxx User SerDes Multiplexer Control Register. The P2020 SerDes lane routing is shown in the following table.
The logical protocols which run on the SerDes lanes are specified by strapping options P2020 CPU read at system powerup.
To obtain a complete overview about all theoretical protocol combinations, please refer to the Freescale "P5020 QorIQ
Integrated Multicore Communication Processor Family Reference Manual", Chapter 3.5.11 "SerDes Lane Assignments and
Multiplexing".
To handle the SerDes configuration in a more comfortable way, Kontron provides the configuration tool “sconf”. “sconf”
provides a very easy way to configure the functionality of the SerDes lanes. Refer to Chapter 6, "U-Boot" for further infor-
mation.
Table 2-6: P2020 SerDes Lane Routing
P2020 SerDes COMe Connector Port
CPLD
Control Line
CPLD
Control Line#
Lane #1 SERDES_TX/RX[1]+/- SERDES_TX/RX[4]+/-
Lane #2 SERDES_TX/RX[2]+/- SERDES_TX/RX[10]+/-
Lane #3 SERDES_TX/RX[3]+/- SERDES_TX/RX[11]+/-