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COMe-P2020 User Guide
6
Table 3-21: 0x011: User Checksum Register......................................................................... 51
Table 3-22: 0x012: UFM Erase Control Register .................................................................... 51
Table 3-23: 0x013: UFM/CPU Control and Status Register....................................................... 52
Table 3-24: 0x080: POST Code Low Byte Register .................................................................. 52
Table 3-25: 0x081: POST Code High Byte Register ................................................................. 52
Table 3-26: 0x084: Debug Low Byte Register ....................................................................... 52
Table 3-27: 0x085: Debug High Byte Register ...................................................................... 53
Table 3-28: 0x280: Status Register 0.................................................................................. 53
Table 3-29: 0x282: Control Register 0 ................................................................................ 53
Table 3-30: 0x284: Device Protection Register ..................................................................... 54
Table 3-31: 0x285: Reset Status Register ............................................................................ 54
Table 3-32: 0x286: Board Interrupt Configuration Register (not implemented!) ......................... 54
Table 3-33: 0x288: Board ID High Byte Register ................................................................... 55
Table 3-34: 0x289: Board and PLD Revision Register ............................................................. 55
Table 3-35: 0x28C: Watchdog Timer Register ....................................................................... 56
Table 3-36: 0x28D: Board ID Low Byte Register .................................................................... 56
Table 3-37: 0x290: LED Configuration Register .................................................................... 57
Table 3-38: 0x291: LED Control Register ............................................................................. 57
Table 3-39: 0x300: Default Boot ROM Location Configuration Register...................................... 58
Table 3-40: 0x301: Default Host/Agent Configuration Register ............................................... 58
Table 3-41: 0x302: Default I/O Selection Register ................................................................ 59
Table 3-42: 0x303: Default Boot Configuration Register......................................................... 60
Table 3-43: 0x304: Default Boot ROM Location Configuration Register...................................... 60
Table 3-44: 0x305: Default SerDes Reference Clock Configuration Register ................................ 60
Table 3-45: 0x306: Default eTSEC2 SGMII Mode Configuration Register ..................................... 61
Table 3-46: 0x307: Default eTSEC3 SGMII Mode Configuration Register ..................................... 61
Table 3-47: 0x308: Default eTSEC1 Width Configuration Register ............................................. 61
Table 3-48: 0x309: Default eTSEC2 Protocol Configuration Register (Reserved, See note!) ............ 62
Table 3-49: 0x30A: Default eTSEC3 Protocol Configuration Register (Reserved, See note!) ............ 62
Table 3-50: 0x30B: Default RapidIO Device ID Register .......................................................... 63
Table 3-51: 0x30C: Default RapidIO System Size Register ....................................................... 63
Table 3-52: 0x30D: Default Core0 Speed Register ................................................................. 63
Table 3-53: 0x30E: Default Core1 Speed Register (Reserved, see note!).................................... 64
Table 3-54: 0x30F: Default SerDes PLL Time-out Enable Register.............................................. 64
Table 3-55: 0x320-0x321: Scratchpad Registers #0-#1 .......................................................... 64
