Altera Nios II C2H Compiler - Manual (Page 105)

Altera Corporation 9.1 4–11
November 2009 Nios II C2H Compiler User Guide
Understanding the C2H View
Loop Latency
As mentioned in Chapter 3, C-to-Hardware Mapping Reference , the loop
latency is a fixed time overhead, incurred each time the accelerator enters
the loop. The loop latency is the number of states needed to set up
conditions for efficient loop iteration.
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It is important to remember that if the accelerator re-enters the
loop multiple times, it incurs the loop latency each time.
Cycles Per Loop Iteration (CPLI)
The CPLI is a measure of the data throughput of a loop. This section lists
the critical loop variable and the assignments in the critical path. The
critical loop variable represents the most significant contribution to the
CPLI value of a loop. In
Example 4–2 , the critical loop variable is crc .
The critical path represents the longest data dependency in the loop. The
CPLI value quantifies the length of the critical path. You can use this
section to help you understand the scheduling and optimize the
algorithm to reduce the CPLI. The assignments shown in this section
contain not only the critical path variable but also all other assignments
that take place on the same states as the critical path variable.
The concept of the critical path might appear confusing at first. However,
if you have a good understanding of the algorithm, it is not difficult to
find the critical path.
Figure 4–4 shows the CPLI report for Example 4–2 . In the CPLI report, a
path is identified by its starting and ending states. In Example 4–2 , as we
will see, the critical path turns out to be states 6 through 11. The report
identifies this path as
6--->11 .