Altera Nios II C2H Compiler - Manual (Page 25)

Altera Corporation 9.1 2–3
November 2009 Nios II C2H Compiler User Guide
Getting Started Tutorial
During the design process with the C2H Compiler, you use the following
tools:
■ Nios II Integrated Development Environment (IDE) – You control
acceleration options for individual functions in the Nios II IDE. The
results of accelerating functions are reported in the Nios II IDE. The
output is an executable linking file (.elf) targeting a Nios II CPU. The
C2H Compiler also invokes SOPC Builder and optionally the
Quartus II software in the background to regenerate the Nios II
system and update the SRAM object file (.sof).
■ SOPC Builder – SOPC Builder manages the generation of C2H logic
and Avalon-MM system interconnect fabric to connect hardware
accelerators to the processor. During the software build process, the
Nios II IDE can invoke SOPC Builder in the background to update
the hardware accelerators when necessary and integrate them into
the Nios II hardware design. The output is a set of hardware
description language (HDL) files (.v or .vhd) and an SOPC Builder
system file (.sopcinfo) defining your system: Nios II processor cores,
peripherals, accelerators, on-chip memory, and interfaces to off-chip
memory.
■ Quartus II software – The Quartus II software compiles and
synthesizes HDL produced by the C2H Compiler and SOPC Builder
tools, along with any other custom logic in your Quartus II project.
During the software build process, the Nios II IDE can invoke the
Quartus II software in the background to recompile the Quartus II
project. The output is a .sof file that includes the updated Nios II
system with accelerators.
OpenCore Plus Evaluation
Hardware accelerator blocks generated by the C2H Compiler support
OpenCore
® Plus evaluation. OpenCore Plus evaluation allows you to use
the C2H Compiler and evaluate the performance of hardware
accelerators in real systems before purchasing a license for the tool. With
Altera's free OpenCore Plus evaluation feature, you can:
■ Verify the functionality of your design, as well as evaluate its size
and speed easily
■ Generate time-limited device programming files for designs that
include megafunctions
■ Program an FPGA and verify your design in hardware
■ Simulate the behavior of an accelerator in your system