Altera Nios II C2H Compiler - Manual (Page 4)

iv 9.1 Altera Corporation
Nios II C2H Compiler User Guide
Contents
Next Steps ............................................................................................................................................. 2–16
Chapter 3. C-to-Hardware Mapping Reference
One-to-One C-to-Hardware Mapping ................................................................................................ 3–1
Arithmetic and Logical Operators ................................................................................................. 3–1
Assignments ...................................................................................................................................... 3–2
Iteration Statements ......................................................................................................................... 3–5
Selection Statements ......................................................................................................................... 3–6
Subfunction Calls ........................................................................................................................... 3–11
Macros and Preprocessing Directives ......................................................................................... 3–13
Variable Declarations .......................................................................................................................... 3–13
Local vs. Non-Local Variables ...................................................................................................... 3–13
Scalar Variables ............................................................................................................................... 3–14
Memory Accesses ................................................................................................................................ 3–15
Indirection Operator (Pointer Dereference) ............................................................................... 3–16
Avalon-MM Master Port Signal Generation .............................................................................. 3–20
Array Subscript Operator .............................................................................................................. 3–26
Structure and Union Operators .................................................................................................... 3–28
Scheduling ............................................................................................................................................ 3–30
Scheduling Concepts for Hardware Accelerators ..................................................................... 3–30
Pointer Aliasing .............................................................................................................................. 3–32
Read Operations with Latency ..................................................................................................... 3–37
Stalling ............................................................................................................................................. 3–39
Loop Pipelining .............................................................................................................................. 3–42
Subfunction Pipelining .................................................................................................................. 3–49
Resource Sharing ................................................................................................................................. 3–51
Chapter 4. Understanding the C2H View
Introduction ............................................................................................................................................ 4–1
Overview ................................................................................................................................................. 4–1
Generation/Compilation Configurations ..................................................................................... 4–1
Resources ................................................................................................................................................ 4–3
Avalon-MM Master Port Resources .............................................................................................. 4–6
Mathematical Operator Resources ................................................................................................. 4–8
Performance .......................................................................................................................................... 4–10
Source Line Number ...................................................................................................................... 4–10
Loop Latency ................................................................................................................................... 4–11
Cycles Per Loop Iteration (CPLI) ................................................................................................. 4–11
Scheduling Information ................................................................................................................. 4–14
Further Reading ................................................................................................................................... 4–19
Chapter 5. Accelerating Code Using the Nios II Software Build Tools Command Line
Creating an Accelerator from the Command Line ........................................................................... 5–1
C2H Performance Metrics .................................................................................................................... 5–2
Chapter 6. Pragma Reference
Introduction ............................................................................................................................................ 6–1