Altera RAM-Based Shift Register - Manual (Page 14)

2–8 Chapter 2: Getting Started
Design Example: Shift Register with Taps
RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide May 2013 Altera Corporation
Quartus II Software Simulator
With the Quartus II Simulator, you can perform two types of simulations: functional
and timing. A functional simulation enables you to verify the logical operation of
your design without taking into consideration the timing delays in the FPGA. This
simulation is performed using only your RTL code. When performing a functional
simulation, add only signals that exist before synthesis. You can find these signals in
the Node Finder by using any of the following Filter options: Registers: pre-synthesis,
Design Entry, or Pins. The top-level ports of megafunctions are found using these
three filters.
In contrast, timing simulation in the Quartus II software verifies the operation of your
design with annotated timing information. This simulation is performed using the
post-place-and-route netlist. When performing a timing simulation, add only signals
that exist after place-and-route. These signals are found with the post-compilation
filter of the Node Finder. During synthesis and place-and-route, the names of the RTL
signals change. Therefore, it may be difficult to find signals from your megafunction
instantiation in the post-compilation filter.
To preserve the names of your signals during the synthesis and place-and-route
stages, use the synthesis attributes keep or preserve. These are Verilog HDL and
VHDL synthesis attributes that direct analysis and synthesis to keep a particular wire,
register, or node intact. Use these synthesis attributes to keep a combinational logic
node so you can observe the node during simulation.
f
For more information about these attributes, refer to the Quartus II Integrated Synthesis
chapter in volume 1 of the Quartus II Handbook.
EDA Simulator
The Quartus II Handbook chapters describe how to perform functional and gate-level
timing simulations that include the megafunctions, with details about the files that are
needed and the directories where the files are located.
f
Depending on which simulation tool you are using, refer to the appropriate chapter in
the
Simulation section in volume 3 of the Quartus II Handbook.
Design Example: Shift Register with Taps
The objective of this design example is to implement and instantiate an
ALTSHIFT_TAPS megafunction built through the Shift Register (RAM-Based)
MegaWizard Plug-In Manager. This example uses a shift register with a data width, w,
of 8 bits, a taps distance, m, of 3, and the number of taps, n, equal to 4. It also
demonstrates how you can tap the data at specific points from the shift register chain.
Design Files
The example design files are available in the User Guides section on the Literature
page of the Altera
® website ( www.altera.com ).