Altera Phase-Locked Loop - Manual (Page 13)

Figure 2: PLL
cclk
Cascading and
adjpllin
Cascading Modes
adjpllin Cascading cclk Cascading
Output Counter 17
Upstream PLL
cclk Port
adjpllin Port
Downstream PLL
Upstream PLL
Downstream PLL
Output Counter 4
The clock input to PLL comes from the clock input multiplexers. The clock input multiplexers provide
multiple clock sources as reference clock inputs for fractional PLL.
Table 8: Reference Clock Inputs for Fractional PLL
Sources Description
coreclkin
Core reference clock from clock network.
adjpllin
Adjacent fractional PLL clock source.
refclkin[0]
Clock source from adjacent PMA triplet LVPECL buffer.
UG-01087
2015.05.04
PLL-to-PLL Cascading 13
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide Altera Corporation
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