Altera Phase-Locked Loop - Manual (Page 18)

Date Version Changes
March 2013 1.2
• Added the “Reference Clock Switchover” section.
• Added the “PLL to PLL Cascading” section.
• Added new parameters for the following features: clock switchover,
PLL cascading, MIF streaming, and PLL settings, in Table 1.
• Added the following new ports: refclk1, extswitch, activeclk, clkbad,
cclk, adjpilin, and cascade_out, in Table 3 and Figure 3.
January 2011 1.1
• Added two new parameters in Table 1.
• Updated Figure 3: ALTERA PLL Ports.
July 2010 1.0 Initial release.
18 Document Revision History
UG-01087
2015.05.04
Altera Corporation Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
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