Altera Phase-Locked Loop - Manual (Page 6)

Altera PLL IP Core Parameters - Cascading Tab
Table 3: Altera PLL IP Core Parameters - Cascading Tab
Parameter Legal Value Description
Create a ‘cascade out’ signal
to connect with a
downstream PLL
Turn on or
Turn off
Turn on to create an output port, which indicates that this
PLL will be used as a source and it connects with a destina‐
tion (downstream) PLL.
Specifies which outclk to be
used as cascading source
Stratix V and
Arria V: 1–18,
Cyclone V: 1–
9
Specifies the cascading source.
Create an adjpllin or cclk
signal to connect with an
upstream PLL
Turn on or
Turn off
Turn on to create an input port, which indicates that this
PLL will be used as a destination and it connects with a
source (upstream) PLL.
PLL Cascading Mode Create an
adjpllin signal
to connect
with an
upstream PLL
or Create a
cclk signal to
connect with
an upstream
PLL
• If you select Create an adjpllin signal to connect with
an upstream PLL, the
adjpllin
signal is created to
connect with an upstream PLL during cascading.
• If you select Create a cclk signal to connect with an
upstream PLL, the
cclk
(5) signal is created to connect
with an upstream PLL during cascading.
Altera PLL IP Core Parameters - MIF Streaming Tab
Table 4: Altera PLL IP Core Parameters - MIF Streaming Tab
Parameter Legal Value Description
Generate MIF file Turn on or
Turn off
Turn on to generate the .mif for the current PLL profile. You
must turn on the Enable dynamic reconfiguration of PLL
parameter in the Settings tab before selecting this function.
The generated .mif contains a PLL profile, and a collection of
physical parameters—such as
M
,
N
,
C
,
K
, bandwidth, and
charge pump—that defines that PLL. You can then load
this .mif into the Altera PLL Reconfig IP core.
Enable Dynamic Phase
Shift for MIF Streaming
Turn on or
Turn off
Turn on to store dynamic phase shift properties for PLL
reconfiguration. You must turn on the Enable dynamic
reconfiguration of PLL parameter in the Settings tab
before selecting this function.
DPS Counter Selection C0–C17, All
C, or M
Selects the counter to undergo dynamic phase shift.
(5) Not supported in Cyclone V devices.
6 Altera PLL IP Core Parameters - Cascading Tab
UG-01087
2015.05.04
Altera Corporation Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
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