Altera Designing With Low-Level Primitives - Manual (Page 39)

Altera Corporation 2–17
April 2007 Designing with Low-Level Primitives User Guide
Primitive Reference
Example 2–12. ALT_OUTBUF_TRI_DIFF Primitive, VHDL Component Instantiation
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;
entity test_outbuf_tri is
port (
datain_h, datain_l : in std_logic_vector (0 downto 0);
oe, outclock : in std_logic;
dataout, dataout_n : out std_logic
);
end test_outbuf_tri;
architecture test of test_outbuf_tri is
component altddio_out
generic (
intended_device_family: STRING;
lpm_type : STRING;
power_up_high : STRING;
width : NATURAL
);
port (
dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
outclock : IN STD_LOGIC ;
oe : IN STD_LOGIC ;
datain_h : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
datain_l : IN STD_LOGIC_VECTOR (0 DOWNTO 0)
);
end component;
signal tmp_out : std_logic_vector (0 downto 0);
signal tmp_oe : std_logic;
begin
DDIO_OUT : altddio_out
generic map (
intended_device_family => "Stratix II",
lpm_type => "altddio_out",
power_up_high => "OFF",
width => 1
)
port map (
outclock => outclock,
oe => tmp_oe,
datain_h => datain_h,
datain_l => datain_l,
dataout => tmp_out
);