Altera Designing With Low-Level Primitives - Manual (Page 20)

1–14 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Low-Level Primitive Examples
Example 1–9 is a more complex example using parameterized Verilog
and the LUT_INPUT and LUT_OUTPUT primitive buffers. This example
creates a LUT function to implement an arbitrary function in a single
LUT. The value of “out” is generated by the
mask signal and uses the
LUT_INPUT and LUT_OUTPUT primitive buffers to build a single logic
cell that implements the functionality given by the
LUT_MASK parameter.
Example 1–9. Parameterized Verilog and LUT_INPUT and LUT_OUTPUT Primitive Buffers
module lut_sub (din,out);
parameter LUT_SIZE = 4;
parameter NUM_BITS = 2**LUT_SIZE;
input [LUT_SIZE-1:0] din;
parameter [NUM_BITS-1:0] mask = {NUM_BITS{1'b0}};
output out;
wire out;
// buffer the LUT inputs
wire [LUT_SIZE-1:0] din_w;
genvar i;
generate
for (i=0; i<LUT_SIZE; i=i+1)
begin : liloop
lut_input li_buf (din[i],din_w[i]);
end
endgenerate
// build up the pterms for the LUT
wire [NUM_BITS-1:0] pterms;
generate
for (i=0; i<NUM_BITS; i=i+1)
begin : ploop
assign pterms[i] = ((din_w == i) & mask[i]);
end
endgenerate
// assign the pterms to the LUT function
wire result;
assign result = | pterms;
lut_output lo_buf (result,out);
endmodule