Altera Designing With Low-Level Primitives - Manual (Page 15)

Altera Corporation 1–9
April 2007 Designing with Low-Level Primitives User Guide
Low-Level Primitive Design
The sclr signal is not inferred by Quartus Integrated Synthesis when
there are a large number of registers with different sclr signals.This
behavior makes it easier for the fitter to successfully route the design. If
you would like to force the use of the
sclr signals, you can use the
following Quartus II synthesis settings.
f
For more details about these and other synthesis settings, refer to the
Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II
Handbook.
■ Force Use of Synchronous Clear Signals—Forces the compiler to
utilize synchronous
clear signals in normal mode logic cells.
Turning on this option helps to reduce the total number of logic cells
used in the design, but might negatively impact the fitting because
synchronous control signals are shared by all the logic cells in a LAB.
■ Allow Synchronous Control Signals—Allows the compiler to utilize
synchronous
clear and/or synchronous load signals in normal
mode logic cells. Turning on this option helps to reduce the total
number of logic cells used in the design, but might negatively impact
the fitting because synchronous control signals are shared by all the
logic cells in a LAB.
f
For more information about inference guidelines for registers and on
secondary control signal inference rules, refer to the Recommended HDL
Coding Styles chapter in volume 1 of the Quartus II Handbook.
Using the DFFEAS Primitive
The DFFEAS primitive allows you to directly instantiate a register in your
design and gives you control over which secondary signals are used. The
DFFEAS primitive instantiations are always adhered to unless the
secondary control signals that you use are not supported by the device
family architecture. If you instantiate a
DFFEAS primitive with
unsupported secondary control signals, they are converted into the
equivalent logic.
1 For an example on instantiation of the DFFEAS primitive, refer
to the Primitive Reference and Synthesis Attributes chapter in this
user guide.
Creating Memory for Your Design
You can create RAM for your design in two ways. The first method
involves creating HDL code that infers a memory function. The second
method involves building a function using the MegaWizard
® Plug-In
Manager and instantiating the resulting custom megafunction variation
file in your design.