Altera Designing With Low-Level Primitives - Manual (Page 28)

2–6 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Primitives
ALT_OUTBUF_TRI
The primitive allows you to make a location assignment, io_standard
assignment, current_strength assignment, termination assignment,
whether or not to use weak pull-up resistor, and allows you to determine
whether or not to enable bus-hold circuitry and/or a
slow_slew_rate
assignment to a tri-stated output pin from a lower-level entity. Table 2–3
explains the ALT_OUTBUF_TRI input and output ports, as well as the
parameter options. If any other parameter is specified, an error will
result.
Example 2–5 shows a Verilog HDL example of an ALT_OUTBUF_TRI
primitive instantiation.
Example 2–5. ALT_OUTBUF_TRI Primitive Instantiation, Verilog HDL
alt_outbuf_tri my_outbuf tri (.i(internal_sig), .oe(enable_sig),
.o(out));
//out must be declared as an output pin
defparam my_outbuf_tri.io_standard = “1.8 V”;
defparam my_outbuf_tri.current_strength =
"maximum current";
defparam my_outbuf_tri.slow_slew_rate = “off”;
Example 2–6 shows a VHDL component declaration for an
ALT_OUTBUF_TRI primitive instantiation.
Example 2–6. ALT_OUTBUF_TRI Primitive Component Declaration, VHDL
COMPONENT alt_outbuf_tri
GENERIC (
IO_STANDARD : STRING :="NONE";
CURRENT_STRENGTH : STRING :="NONE";
SLOW_SLEW_RATE : STRING :="NONE";
LOCATION : STRING :="NONE";
ENABLE_BUS_HOLD : STRING :="NONE";
WEAK_PULL_UP_RESISTOR : STRING :="NONE";
TERMINATION : STRING :="NONE";
SLEW_RATE:INTEGER := -1
);
PORT (
i : IN STD_LOGIC;
oe : IN STD_LOGIC;
o : OUT STD_LOGIC
);
END COMPONENT;