Altera Designing With Low-Level Primitives - Manual (Page 47)

Altera Corporation 2–25
April 2007 Designing with Low-Level Primitives User Guide
Primitive Reference
Example 2–16. ALT_BIDIR_DIFF Primitive, VHDL Component Declaration
component ALT_BIDIR_DIFF
generic (
IO_STANDARD : STRING := "none";
LOCATION : STRING := "none";
ENABLE_BUS_HOLD : STRING := "none";
WEAK_PULL_UP_RESISTOR : STRING := "none";
INPUT_TERMINATION : STRING := "none";
OUTPUT_TERMINATION : STRING := "none" ;
TERMINATION : STRING := "none"
);
port (
bidirin : inout std_logic;
oe: in std_logic;
io : inout std_logic;
iobar : inout std_logic
);
end component;
ALT_BIDIR_BUF
This primitive allows you to create a location assignment, io_standard
assignment, drive strength (current strength) assignment and/or
slew_rate assignment to the bidirectional pin connected to an
altddio_bidir megafunction. The legal configuration of the primitive and
the complete list of supported parameters are described in
Table 2–10 . If
the primitive is used in any other configuration or with any other
parameter, an error will be given.
Table 2–10. ALT_BIDIR_BUF Ports and Parameters (Part 1 of 2)
Port/Parameter Description/Value
Input Port
oe Connect this port to the oe_out port of the altddio_bidir megafunction.
Bidirectional Port
bidirin Connect this port to the padio port of the altddio_bidir megafunction. The
padio port should not have any other fan-outs.
io Connect this port to the device’s bidir pin or an entity bidir port. There
must be no logic between the io port and the chip bidir port.
Parameter Name
io_standard Any legal I/O standard value.
current_strength Any legal value of the current_strength_new QSF assignment.
location Any legal pin location for the current device.