Inferring ram functions from hdl code, Using the megawizard plug-in manager – Altera Designing With Low-Level Primitives User Manual

Page 16

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1–10

Altera Corporation

Designing with Low-Level Primitives User Guide

April 2007

Low-Level Primitive Examples

Inferring RAM Functions from HDL Code

To infer RAM functions, synthesis tools detect sets of registers and logic
that can be replaced with the altsyncram or lpm_ram_dp megafunctions,
depending on the targeted device family. The Quartus II software usually
does not infer very small RAM blocks because they typically are
implemented more efficiently by using the registers in regular logic.

If your design contains a RAM block that your synthesis tool does not
recognize and infer, the design might require a large amount of system
memory, which can potentially cause run-time compilation problems.

f

For RAM inference guidelines, refer to the Recommended HDL Coding
Styles
chapter of the Quartus II Handbook.

Using the MegaWizard Plug-In Manager

You can use the MegaWizard Plug-In Manager to create RAM functions.
The MegaWizard Plug-In Manager, located in the Tools menu in the
Quartus II software, allows you create or modify design files that contain
custom megafunction variations, which you can then instantiate in a
design file.

The GUI-based interface of the MegaWizard Plug-In Manager provides
an easy and intuitive interface that allows you to parameterize complex
functions such as memory. However, there are cases, particularly with
memory, where you simply want to modify a small component of the
megafunction. For example, your design can call for two types of memory
functions: a 32, 8-bit word single-port memory function and a 64, 8-bit
word single-port memory function. In this scenario, you can use the
MegaWizard Plug-In Manager to create one function and then use the
instantiation from the wizard-generated file to directly instantiate the
second variation. However, directly instantiating memory functions
should only be used when the modifications to the functions are minimal.

Example 1–6

shows a Verilog example for a 32, 8-bit word single-port

memory function.

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