Altera DSP Development Kit, Stratix V Edition - Manual (Page 36)

6–12 Chapter 6: Board Test System
Using the Board Test System
DSP Development Kit, Stratix V Edition July 2013 Altera Corporation
User Guide
Performance Indicators
These controls display current transaction performance analysis information collected
since you last clicked Start:
■ Write and Read performance bars—Show the percentage of maximum theoretical
data rate that the requested transactions are able to achieve.
■ Write (MBps) and Read (MBps)—Show the number of bytes of data analyzed per
second. The QDR II+ buses are 18 bits wide for both read and write, and the
frequency is 550 MHz double data rate (1100 Mbps per pin), equating to a
theoretical maximum bandwidth of 2475 MBps, and 4950 MBps for simultaneous
read and write.
1
Performance figures are based on a 125-MHz input clock from
programmable oscillator U46. Using the
“The Clock Control” on page 6–23
to adjust the frequency changes the circuit speed in real time and the
QDR II+ tab performance indicators, which are capped at 100% for
increased frequencies. Physical layer speeds equal the oscillator U46 CLK0
frequency times the input PLL multiplier ratio. The default is 550 MHz
(125 MHz × 4040) or 1100 Mbps per pin. Changing the oscillator U46 CLK0
frequency to 100 MHz changes the circuit speed to 440 MHz or 880 Mbps
per pin. Typically you need to reset the QDR II+ design after changing the
clock frequency.
Error Control
The Error control controls display data errors detected during analysis and allow you
to insert errors:
■ Detected errors —Displays the number of data errors detected in the hardware.
■ Inserted errors —Displays the number of errors inserted into the transaction
stream.
■ Insert Error —Inserts a one-word error into the transaction stream each time you
click the button. Insert Error is only enabled during transaction performance
analysis.
■ Clear —Resets the Detected errors and Inserted errors counters to zeros.
Number of Addresses to Write and Read
The Number of addresses to write and read control determines the number of
addresses to use in each iteration of reads and writes.
Data Type
The Data type control specifies the type of data contained in the transactions. The
following data types are available for analysis:
■ PRBS —Selects pseudo-random bit sequences.
■ Memory —Selects a generic data pattern stored in the on chip memory of the
Stratix V GS device.
■ Math —Selects data generated from a simple math function within the FPGA
fabric.