Altera PowerPlay Early Power Estimator - Manual (Page 38)

3–24 Altera Corporation
PowerPlay Early Power Estimator For Arria GX FPGAs May 2008
PowerPlay Early Power Estimator Inputs
Phase-Locked Loops (PLLs)
Arria GX devices feature enhanced, LVDS, and fast PLLs for general
usage. If you are using dedicated transmitters or receivers and are using
an LVDS PLL to implement serialization or deserialization, specify an
LVDS PLL and enter power information in the PLL section.
1
When a fast PLL drives LVDS hardware, it is referred to as an
LVDS PLL. LVDS PLLs drive LVDS clock trees and DPA buses
at the VCO frequency (0 to 840 MHz). If an LVDS PLL drives
LVDS hardware only, enter the appropriate VCO frequency and
specify an output frequency of 0 MHz. If the LVDS PLL also
drives a clock to a pin or to the core, specify that clock frequency
as the output frequency (0 to 550 MHz).
Each row in the PLL section represents one or more PLLs in the device.
You need to enter the maximum output frequency and the VCO
frequency for each PLL. You must also specify whether each PLL is an
LVDS, fast or enhanced PLL.
Table 3–8 describes the values that need to
be entered in the PLL section of the PowerPlay Early Power Estimator.
Table 3–8. PLL Section Information
Column Heading Description
Module Enter a name for the PLL in this column. This is an optional value.
PLL Type Select whether the PLL is an LVDS, fast or enhanced PLL.
# PLL Blocks Enter the number of PLL blocks with the same specific output frequency and VCO
frequency combination.
# DPA Buses Enter the number of dynamic phase alignment (DPA) buses in use. DPA is only
available for LVDS PLLs.
Output Frequency (MHz) Enter the maximum output frequency (f
MAX
) of the PLL in MHz. The maximum
output frequency is reported in the PLL Usage column of the Quartus II Compilation
Report. In the Compilation Report, select Fitter, and click Resource Section.
Select PLL Usage, and click Output Frequency.
If there are multiple clock outputs from the PLL, choose the maximum output
frequency listed. The output frequency is the same as the VCO frequency for LVDS
PLLs used as part of a SERDES.
VCO Frequency (MHz) Enter the frequency of the voltage controlled oscillator in MHz. The VCO frequency
is reported in the Nominal VCO frequency row of the Quartus II Compilation Report.
In the Compilation Report, select Fitter, and click Resource Section. Select PLL
Summary, and click Nominal VCO frequency.
Total Power (W) This shows the estimated power in W, based on the maximum output frequency
and the VCO frequency you entered. This value is calculated automatically.
User Comments Enter any comments. This is an optional entry.