Altera PowerPlay Early Power Estimator - Manual (Page 40)

3–26 Altera Corporation
PowerPlay Early Power Estimator For Arria GX FPGAs May 2008
PowerPlay Early Power Estimator Inputs
Figure 3–17. PLL Section in the PowerPlay Early Power Estimator
Clocks
Arria GX devices have a total of 48 clock domains available that can be on
either a global or regional clock network. There are 16 global clocks and
8 regional clocks per quadrant for a total of 32 regional clocks.
Each row in the Clocks section represents a clock network or a separate
clock domain. You must enter the clock frequency (f
MAX
) in MHz, the
total fanout for each clock network used, the global clock enable
percentage, and the local clock enable percentage.
Table 3–9 describes the
parameters in the Clocks section of the PowerPlay Early Power
Estimator.
Table 3–9. Clock Section Information (Part 1 of 2)
Column Heading Description
Domain Enter a name for the clock network in this column. This is an optional value.
Clock Freq (MHz) Enter the frequency of the clock domain.
Total Fanout Enter the total number of flip flops and RAM, DSP, and I/O blocks fed by this clock. The
number of resources driven by every global clock and regional clock signal is reported
in the Fan-out column of the Quartus II Compilation Report. In the Compilation Report,
select Fitter and click Resource Section. Select Global & Other Fast Signals and
click Fan-out.