Altera Stratix V Advanced Systems - Manual (Page 20)

5–2 Chapter 5: Board Test System
Preparing the Board
Stratix V Advanced Systems Development Kit February 2013 Altera Corporation
User Guide
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
The Power Monitor button starts the Power Monitor application that measures and
reports current power and temperature information for the board. Because the
application communicates over the JTAG bus to the MAX V device, you can measure
the power of any design in the FPGA, including your own designs.
1 The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
® II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, follow these steps:
1. Connect the mini-USB cable to the board.
2. Ensure that the board DIP switches are set to default positions as shown in the
“Factory Default Switch and Jumper Settings” section starting on page 4–2 .
f For more information about the board’s DIP switch and jumper settings,
refer to the
Stratix VAdvanced Systems Development Board Reference Manual .
1
FPP x8 mode must be enabled for the BTS functionality to work.
3. Turn on the power to the board. By default, the board loads FPGA1 with the
design stored in the factory hardware 0 portion of flash memory and FPGA2 with
the factory hardware 1 portion of flash memory. If your board is still in the factory
configuration, the design loads the FPGA1 GPIO tests.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.
Running the Board Test System
To run the application, navigate to the <install
dir>\kits\stratixVGX_5sgxea7nf45_as\examples\board_test_system directory and
run the BoardTestSystem.exe application.
1 On Windows, click Start > All Programs > Altera > Stratix V Advanced Systems
Development Kit
<version> > Board Test System to run the application.